Advice on OOP hardware I/O code structure

2026-08-30T19:00:00.815000Z

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Advice on OOP hardware I/O code structure

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Advice on OOP hardware I/O code structure

2026-08-27T13:19:03.932000Z

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Advice on OOP hardware I/O code structure

2025-10-31T03:00:14.318000Z

Call 10 FB instances. Connect Motor_1_Fault to the i_xHW_FaultDetected pin of FB 1, Motor_2_Fault to FB 2...

By doing this, your FB will be flexible. The programming will be smooth like a perfect Drift Boss, instead of "hitting the wall" because it can't be reused!

Advice on OOP hardware I/O code structure

2024-09-30T12:10:32.956000Z

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Advice on OOP hardware I/O code structure

2023-04-18T17:54:30.037000Z

There's also this method of declaring a function block instance for each I/O channel, seems like it would accomplish what you're trying to do quite nicely: https://help.codesys.com/api-content/2/codesys/3.5.13.0/en/_cds_configuring_devices_mapping_ios/#mapping-a-device-input-to-a-function-block-instance

Advice on OOP hardware I/O code structure

2023-04-11T03:12:28.194000Z

I am the guy from the Stackoverflow answer. Let me attempt to give you a few more breadcrumbs.

You are likely to want to achieve any combination of these goals.

Make your control logic independent from your hardware
Avoid hard-coded hardware addressing.
Allow several instances of whichever device you control (e.g. motor)
Make your code portable (for me, this means CODESYS and TwinCAT).

I have found only one sane way to check all these boxes. This way involves not trying to achieve all these goals within the same function block. I have roughly four layers (that each correspond to separate libraries/projects):

Function blocks that represent actual hardware devices (such as individual I/O cards). They define inputs/outputs as incomplete addresses (%I or %Q). The incomplete addresses can be coded against even though they are only to be mapped in the final project that uses the library.
Function blocks that represent the control logic. They have their own input/output structures, which are normal variables. They use no I/O addresses, and no hardware device function blocks.
"Electrical design" function blocks, that inherit from control logic function blocks, but also declare hardware function blocks as well as methods that copy the hardware inputs to control inputs, and control outputs to hardware outputs. Each function block matches a specific electric drawing. Only in this function block is there a relationship between the hardware and the control logic, which makes sense because the electrical design is not hardware-independent (the coupling happens at the "right place").
Projects, that use these (reusable) hardware-dependent function blocks, and map the incomplete addresses.

You can see how each layer has a precise role to play in abstracting away different things, which allows different kinds of reuse (control logic reuse, hardware device reuse, full subsystem reuse) to happen independently.

We can have several hardware implementations (electrical designs) for the same control logic. We can have inputs and outputs that have different formats in the control logic vs. hardware (think analog scaling, reading/writing ENUM values as bit groups, etc.).

I/O function blocks can be as simple as this :

FUNCTION_BLOCK BECKHOFF_EL1002
VAR_INPUT
  in AT %I* : IO_2CH1_BIT;
END_VAR

The IO_2CH1_BIT structure is just this :

TYPE IO_2CH1_BIT :
STRUCT
  ch1 : BIT;
  ch2 : BIT;
END_STRUCT
END_TYPE

Per-project mapping is super-easy, because you are mapping an I/O card's memory to a function block that represents the same I/O card (and can have the same instance name as the I/O card in your project tree). The relationship between hardware and control logic variables is implemented at a reusable layer, so we only have to test and debug once for each hardware design. Any technician with a rough understanding of the IDE can create a project and map the I/O without any knowledge of the control logic.

In other words, we achieve hardware-independence of the control logic, control-logic independence of the project, while retaining reusable, programmatic use of hardware-dependent features neither the project nor the control logic know anything about.

Advice on OOP hardware I/O code structure

2023-04-06T01:43:13.728000Z

I'd prefer programming individual signals over BYTE or WORD/ DWORD assigned boolean channels. Usually individual channel assignment makes your code read way easier both at the hardware IO mapping and in the FB or PRG itself. The slight cost of declaring more channels usually adds tremendous added value for well readable code. The adagio in modern days is readability over compact programming. PS read up on PLCOPen programming style guidelines, they forbid you from using of direct adressing.

Advice on OOP hardware I/O code structure

2023-04-05T21:18:28.918000Z

With 5) you mean using the I/O mapping tab and mapping the full path name to a hardware channel/address?

Im doing this right now but using the AT command for mapping the full Input or Output module, not just a single channel.

So I habe an IO Struct, which contains for example

Value : Bool
Unit : String(80);

And another struct for the module, with:

Channel : Array[0..13] Of IO_DUT
Input At %IW0 : Word;

Im instancing the module struct as a Var_in_out in a program. With that I didn't touched the I/O mapping tab.

In order to avoid the at command I need to define

Input_1 : Bool;
Input_2 : Bool;
...

and map each variable to one input channel via the I/O mapping tab, right? Or do you have a different procedure in mind?

Advice on OOP hardware I/O code structure

2023-04-05T18:03:00.074000Z

VAR_IN_OUT is technically a pointer so yes it is absolutely the way to go

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