Welcome to our new forum
All users of the legacy CODESYS Forums, please create a new account at account.codesys.com. But make sure to use the same E-Mail address as in the old Forum. Then your posts will be matched. Close

SPI _diMode with Unreasonable Values

bwayt
2021-09-07
2 days ago
  • bwayt

    bwayt - 2021-09-07

    Hello all,
    I have made progress on SPI comm to my buffer board (hooray!), in that there is a decipherable SCLK and MOSI signal. However, I've noticed that the MOSI signal is bit shifted to the left by one; for example, trying to send 72 (#01001000) instead shows on the oscilloscope as #10010000.
    After a bit of research the consensus seemed to be that it is a SPI mode issue, and indeed, when I check my SPI parameters it shows a diMode = 4; which makes no sense. From the datasheet I can see that I need to be in Mode 0, which I have set it to before I go online; but when online, it sets diMode to 4. I can't decipher this. Does anyone have any experience with this issue?
    Link to the buffer board datasheet: https://lsicsi.com/datasheets/LS7366R.pdf
    EDIT: I forced diMode = 0 and still see the same results, so this likely isn't the issue.

     

    Last edit: bwayt 2021-09-07
  • gised-link

    gised-link - 2021-09-08

    Hi,

    First, do you have a logic analyser (may be integrated inside your oscilloscope)? Such a tool is a game changer when it comes to debug UART/I2C/SPI/... signals. If you can provide some pictures of the SPI signals, this will be perfect.

    As documented in page 7 of your datasheet, MOSI information are valid/read on the rising edge of the CLK signal. Be sure to "output" some signals with the correct timing (you can do it without slave connected). instead of Mode 0, try another mode just to see what happens on your scope. If it is impossible to set another mode, try to reduce the communication speed. Maybe this settings force the mode? Maximum SPI slave speed seems to be 5 MHZ, try with 500kHz.

    In my opinion, with the information given, the mode is definitely the issue...

     

    Last edit: gised-link 2021-09-08
    • bwayt

      bwayt - 2021-09-08

      I figured out what was wrong...dumb me :X
      I forgot that it was shifting out on the falling edge and therefore MOSI would lead SCLK; so the original signal is correct πŸ˜…
      Anyways. Still don't know why SPI mode shows 4 at runtime, but it's obviously still on mode 0. Problem solved!

       
      πŸ‘
      2

Log in to post a comment.