SFC: Tranistion time/duration between Steps

2020-11-09
2020-11-09
  • justthefacts77 - 2020-11-09

    Hey Folks, if I have a Step--> Step transition that is "true" (not conditional), what determines the time from one Step to the next?

    Is there a Master system clock somewhere defined that SFC utilizes?

    My frame of reference is a "Finite State Machine" in say an FPGA that uses a Master State clock.

     

    Last edit: justthefacts77 2020-11-09
  • dFx

    dFx - 2020-11-09

    Reading how SFC handles transitions and how step actions are performed in the help is quite a mandatory step.

    At least one scan cycle time, plus every seconds it takes for your previous exit action and next entry action and next continuous action to be performed.

     

    Last edit: dFx 2020-11-09

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