Post by danwoodlock on RPI Zero w - Edge gateway cant install ^{CODESYS Forge talk (Post)}
Hello all, First post. I recently acquired an RPI zero W from amazon, and have been using it with Codesys v3.5 SP19 patch 2. I first got it working yesterday, and after installing the runtime on the Pi, I was prompted to install the edge gateway. Installation of the edge gateway failed because of unsupported architecture, undeterred I was able to connect to the pi and program as I wanted. The issue I've noticed is that if I do not load anything to the pi overnight, I can then no longer connect to the pi and download, although I can still ping it from my pc. I found that if I power cycle the PI, I am then able to connect again, and it works as normal. I did some googling and found instances where people recommended downloading the newest edge gateway, which brings me here. Wondering if there are any suggestions, or if this is a known issue. I actually tried installing all 3 versions of edge gateway for science, but all fail with the same message. Thanks -Dan
Last updated: 2023-09-13

Post by sturmghost on Initialization of visualization variables and cyclic code execution ^{CODESYS Forge talk (Post)}
I'm looking for a smart and short way to implement initialization of visualization variables depending on the visualization input. For an easy example consider a rectangle which rests at XPos := 0 when the input state is false and at XPos := 50 when the input state is true. My visualization variables look like this: VAR_IN_OUT State : BOOL; END_VAR VAR XPos : INT; END_VAR I put this rectangle via a visualization frame element into another visualization and link a frame reference variable with the state to it. If the variable is true, the rectangle should rest at XPos := 50 and false at XPos := 0 at visualization init but how should I assign the 50 or 0 to the internal visualization variable XPos? I would need some init-methode for the visualization but I dont want a global init-method for such tasks. I want to do it inside of the visualization element but I can't see any solution for this? It would be good to be able to define ST-code within the visualization element which runs cyclic at each VISU_TASK task-cycle then I could just check the input state and change the XPos accordingly. Does someone have a solution?
Last updated: 2023-10-01

Post by mondinmr on Jitter problems on imx8 ^{CODESYS Forge talk (Post)}
We are experiencing serious jitter issues on an ARM64 imx8. Until now, on rpi and beaglebone derivatives, and on Intel, we never encountered jitter issues unless they were already present on the device. In this case, as can be seen from the attached graph, we have excellent maximum latency. The cyclictest on the isolated core dedicated to IEC CODESYS tasks shows a latency of 37µs, with an average of 14µs. Usually, on all other devices, with an RT kernel, with the appropriate parameters to avoid frequency throttling, with properly managed IRQs, and with the disabling of large page sizes, the jitter measured by CODESYS is very close to the cyclictest latency. However, on this imx8, we are noticing a fluctuating value of +/- 300µs that seems to be added to this latency, as if something occasionally miscalculates the sleep times by exactly +/- 300µs. Two screenshoot attached. - Result of cyclictest - Jitter on CODESYS Tasks are assigned to isolated core!
Last updated: 2023-10-18

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