Diff of / szl4p3-prj,szl4p3,CDS/ABB_AC800_PEC/Plc Logic/APP/00 System/01 Global Variables/Interface/TS_TxBSW_HW_Out_OpToBSW/svnobj [000000] .. [r2]  Maximize  Restore

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(*‚This file is auto-generated by the CODESYS IDE extension package.*Do not edit manually.*):TYPE TS_TxBSW_HW_Out_OpToBSW:STRUCTD    FPGA_bDO_01           :  BOOL;D    FPGA_bDO_02           :  BOOL;D    FPGA_bDO_03           :  BOOL;D    FPGA_bDO_04           :  BOOL;D    FPGA_bDO_05           :  BOOL;D    FPGA_bDO_06           :  BOOL;D    FPGA_bDO_07           :  BOOL;D    FPGA_bDO_08           :  BOOL;D    FPGA_bDO_09           :  BOOL;D    FPGA_bDO_10           :  BOOL;|    FPGA_bEna_PWM1        :  BOOL;      // Enable PWM output 1|    FPGA_bEna_PWM2        :  BOOL;      // Enable PWM output 2–    FPGA_mPWM1            :  LREAL;     // Modulation index of PWM output 1 –    FPGA_mPWM2            :  LREAL;     // Modulation index of PWM output 2!END_STRUCT"END_TYPE#$"UniqueIdGenerator%27ÐÐÐEÐÐ	
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