Isolate CODESYS runtime to a single core

Runtime 🇬🇧
autojay
2021-10-09
2021-10-17

  • autojay - 2021-10-09

    Hi everyone

    I have applied an RT kernel on my raspberry pi. Now I would like to isolate the CODESYS runtime to run on one core. How do I do that? I checked running processes using the htop command and found multiple instances of CODESYS runtime. How do I isolate them all into a single core?

    I've been following this guide here but couldn't it working: http://www.comfilewiki.co.kr/en/doku.php?id=comfilepi:improving_real-time_performance:index

     
more posts ...

  • autojay - 2021-10-14

    Thanks. Would this have the same effect as using the taskset command on the CODESYS runtime?

    And how do I set the CODESYS runtime to run at high priority?

     

  • mondinmr

    mondinmr - 2021-10-14

    I make a little patch to /etc/init.d/codesyscontrol

      ....
    do_status
    if [ $? -eq 0 ]; then
        rm $PIDFILE
        echo "Error: Failed to start codesyscontrol"
        exit 1
    else
        PID=$(cat $PIDFILE)
        taskset -p 1 $PID >>/root/codelog.txt
        renice -n -20 -p $PID >>/root/codelog.txt
        tuna --threads $PID --priority=RR:99
        IRQBALANCE_BANNED_CPUS=3 irqbalance --foreground --oneshot
        echo 0 > /proc/sys/kernel/numa_balancing
        echo never > /sys/kernel/mm/transparent_hugepage/enabled
        echo 0 > /sys/kernel/mm/ksm/run
        echo "codesyscontrol started"
    fi
   ....

    I use a RT preempt patched kernel. (Starting from 5.15 no more patch are needed, RT is merged in mainline and you need only configure and rebuild)
    - taskset move codesys to core 1 (You can select core for runtime from Task Group in Task configuration, I use 0)
    - renice set nice level to maximum (-20)
    - tuna set scheduler type RR and priority to 99 (Maximum on realtime kernel)
    - IRQBALANCE_BANNED_CPUS=3 irqbalance --foreground --oneshot
    turn off interrupts from cores 0 and 1 (mask 0x03)
    - the other options may change between various distros, and could improve jitter.

    On a rpi4 on native ethernet I reached a jitter < 100us (In last test < 68us in one hour), on a rpi3 is not possible due ethernet via USB.

    In kernel command line (/boot/cmdline.txt) I add isolcpus=0,1 to isolate core 0 and 1 from OS management.

     
    👍
    1

    Last edit: mondinmr 2021-10-14

    • autojay - 2021-10-15

      Thanks😄! I'm using the single core version

      In your example above, does this mean that if you use IRQBALANCE_BANNED_CPUS command, CODESYS would not be able to handle any interrupt events of the controller?

      Attached is the result of applying your solution. It seems core 2 still empty. I expect CODESYS would run there. Perhaps because I'm using a single core version and CODESYS always default to core 0.

      In my second attempt, I set taskset to core 0 and set isolcpus=0 in cmdline. I guess it works? But the other core usages are wee bit high for just kernel usage....

       

      Last edit: autojay 2021-10-15
      Thumbnail
      Isolated core 1.PNG
      Thumbnail
      secondAttempt.PNG

      • Ingo

        Ingo - 2021-10-15

        AFAIK it just means, that the interrupts are not calculated on those CPUs.
        When the other CPU(s) are not blocked, and have enough time, it has no
        negative effect on the interrupt performance. It might even have positive
        effects, as interrupts are not blocked by high priority realtime tasks of
        CODESYS.

        So this setup sounds really great!

         
        👍
        1
        alternate

        • autojay - 2021-10-17

          I'm using the single core CODESYS version. Doesn't that mean the interrupt will also occur in the same core?

           

Log in to post a comment.